To avoid dealing with the mind-numbing array of brain-damaged gotchas real
computer architectures lay in the OS implementor's path, the hardware
architecture described here is a combination of generic computer-architecture
features; the whole is not representative of any real computer architecture.
However, some architectural features, particularly the idea of making
everything accessible by mapping into Primary Store, are based on Digital
Equipment Corp.'s Compaq's HP's PDP series of minicomputers.
There are four hardware components in the architecture: the CPU, the primary store, a disk, and a terminal. Of these four components, the primary store can be thought of as being the main component because all other components in the architecture are accessible through primary store.
Primary store is represented as an array of words. The index associated with each word is also known as the word's address. The arrays are indexed as they are in C: starting from zero and increasing by 1 for each successive array element.
Primary store is partitioned into three contiguous subarrays known as the the system space, the user space, and the device space:
These three areas are called “spaces” to emphasize that they are part of primary store.
Each space is defined by three constants: sBase, sSize, and
sTop, where s is one of system, user, or device.
The constant values represent
Base: The lowest accessible address in the associated space.
Size: The number of words in the associated space.
Top: One more than the highest accessible address in the
associated space; that is sTop = sBase + sSize.
systemBase is the lowest accessible address in primary store and
deviceTop is one more than the highest accessible address in primary
store. Note also that systemTop == userBase and userTop ==
deviceBase.
User Space is divided into 32 page frames, where each page frame consists of 32 consecutive words of user space. Page frames are numbered from 0 to 31 with page frame 0 starting at primary store address 1024 and page frame 31 ending just before address 2048.
The hardware uses the contents of five of the CPU registers to control various aspects of process execution; the hardware ignores the contents of the remaining eleven registers. The arrangement of registers in primary store is
The five registers used by the hardware are (the constant name in parenthesis is the address of the register)
BaseRegister) TopRegister) IARegister) PCRegister) PSRegister) The operating system should preserve the CMPR bits (bits 1, 2, and 3) across context switches, but should otherwise ignore them.
The clock is controlled by a set of two clock registers mapped into a group of two words in device space:
The constants Hardware.Address.clockRegister and
Hardware.Address.countdownRegister give the device-space addresses of
the associated clock registers.
The function of each clock register is
Writing a non-positive integer to the countdown register cancels any countdown currently in progress. If no countdown is in progress, writing a non-positive integer to the countdown register has no effect.
The constant Hardware.Address.haltRegister gives the device-space
addresses of the halt register.
Writing a value, any value, into the halt register ends simulator execution.
Hardware.Address.pageFramesInUserSpace elements; each array element of
the page table is a page-table entry. The i-th element in the
page table corresponds to the i-th page fame in user space, 0
pageFramesInUserSpace. The fields in a
page-table entry are
All fields can be manipulated by the operating system. The hardware also
automatically sets accessed_at and modified_at on each reference
to valid page-table entries.
The size of the disk is fixed; that is, the number of disk blocks in the disk
does not change. The constant
Hardware.Disk.blockCount gives the number of blocks in a disk. The size
of each disk block is also fixed; all disk blocks in a disk have the same size.
The constant Hardware.Disk.blockSize gives the
number of words in a disk block.
A disk is controlled through a set of four disk registers mapped into a group of four words in device space:
The constants diskCommandRegister, diskBlockRegister, diskAddressRegister, and diskStatusRegister give the
device-space addresses of the associated disk registers.
The function of each disk register is (the constant name in parenthesis is the Device-Space address of register)
diskCommandRegister)
Writing the value Hardware.Disk.readCommand to the disk command register
initiates disk input: the disk block at the index contained in the disk block
register is moved from the disk to primary store starting at the address
contained in the disk address register.
Writing the value Hardware.Disk.writeCommand to the disk command register
initiates disk output: the data from the sequence of words starting at the
address given in the disk address register and continuing through the size of a
disk block is copied from primary store and written to the disk block at the
index contained in the disk block register.
Any value other than readCommand or writeCommand written to the disk
command register is interpreted as an illegal command code. The disk command
register is a write-only register.
diskBlockRegister)diskAddressRegister)diskStatusRegister)Hardware.Status.ok | command completed successfully |
Hardware.Status.badCommand | unrecognized command |
Hardware.Status.badBlockNumber | bad disk-block number |
Hardware.Status.badAddress | bad primary-store address |
The constants Hardware.Address.terminalCommandRegister, Hardware.Address.terminalDataRegister, and Hardware.Address.terminalStatusRegister give the Device-Space
addresses of the associated terminal registers.
The function of each terminal register is (the constant name in parenthesis is the Device-Space address of register)
terminalCommandRegister)
Writing the value Hardware.read.device to the Terminal Command Register initiates
terminal input: the next 8-bit character to arrive from the terminal is
stored in byte 0 of the Terminal Data Register.
Writing the value Hardware.write.device to the Terminal Command Register initiates
terminal output: the contents of byte 0 in the Terminal Data Register is sent
to the terminal.
A terminal-io command begins as soon as a command is written to the command register, using the value contained in the data registers (if writing). Once a command is started, writing a new value into the data register has no effect on the in-progress operation.
Any value other than Hardware.read.device or Hardware.write.device written to the terminal
command register is interpreted as an illegal command code. The Terminal
Command Register is a write-only register.
terminalDataRegister)terminalStatusRegister)
Hardware.Status.okcommand completed successfully Hardware.Status.badCommandunrecognized command
vmemBase (inclusive) to vmemTop
(exclusive). A process need not occupy all its process address space; if it
does not, then any attempt to access an address in the unoccupied area of
the process address space should cause an invalid address interrupt.
A process address space is broken up into 64 pages, where each page
is a contiguous sequence of 32 words. The pages are numbered from 0 to 63,
where page 0 contains address vmemBase and page 63 contains address
vmemTop - 1.
Given an 11-bit virtual address va, the leftmost 6 bits of va
determine the page number associated with va; the rightmost 5
bits of va determine the page offset within the page at which
the word addressed by va lies.
The physical process-address space comprises the 1024 words making up
User Space. The valid addresses in a physical process address space
range from userBase (inclusive) to userTop (exclusive). A process
need not occupy all its physical process address space; if it does not, then
any attempt to access an address in the unoccupied area of the physical process
address space should cause an invalid address interrupt.
A physical address is interpreted as the 10-bit address of a word in user space and is not further broken down into component values.
va issued by the CPU is run through the Memory Management Unit
(MMU) to determine where - or if - the page holding va resides in user
space.
Upon receiving the virtual address va, the MMU looks for a
process-table entry having the following characteristics:
va matches pageNumber.
If such a page-table entry exists, the MMU translates va into a physical
address in user space; otherwise the MMU throws an invalid address
interrupt. When the MMU throws an invalid address interrupt, the PC is
reset to point to the instruction issuing the invalid address.
If a user process is not executing under virtual memory, then every address issued by the CPU is used to access user space directly without translation.
The defined interrupts are (the name in parenthesis is the identifying value):
Hardware.Interrupt.illegalInstruction)Hardware.Interrupt.reboot)Hardware.Interrupt.systemCall)Hardware.Interrupt.invalidAddress)Hardware.Interrupt.disk)Hardware.Interrupt.terminal)Hardware.Interrupt.countdown)
A device begins an operation as soon as a value is written into its Command Register. The device copies the values stored in the argument registers into internal registers at the start of the operation; the argument registers may be rewritten without effecting the operation in progress. Remember:
A device begins an operation as soon as a value is written into its Command Register.
The appropriate interrupt (disk or terminal) is raised when the operation in progress ends. The contents of the Status Register for the operation in progress is undefined until the interrupt is raised. Writing a value into a Command Register always results in an interrupt, even when the status indicates an error.
Writing a value into a Command Register always starts a new operation. If an operation is in progress when a value is written into the Command Register, it is cancelled and a new operation is started. This behavior occurs whether or not the new operation succeeds or fails.