Operating Systems Lecture Notes

25 January 2012 • Hardware Architectures

---

Outline

• Hardware Architectures
• Logical Organization
  • CPUs
  • Register Set
  • The Address Space
  • Interrupts and exceptions.
• Device Access

Hardware Architectures

• The hardware architecture is the arrangement of hardware components into a system.
• The system architecture is the hardware + software.
  • Sometimes just the software.
  • The abstract machine definition.
• For our purposes, the hardware components are important.
  • Their interconnections, not so much.

So What?

• The hardware
  • provides the raw material for OS resources, and
  • actually does something in the physical world.
• The influence is not always hardware → software.
  • Design hardware with an eye towards the software it will run.

Logical Organization

• The hardware is organized into a bus architecture

  

• This is an high-level diagram.
  • Interconnections are more complicated.
  • Lots of other possible components.

CPUs

• The central processing unit (CPU) is the “brain” in “powerful electronic brain”.

  

Register Set

• The CPU has a set of n w-bit registers called the register set.
  • Typically n = 8 to 32 and w = 8, 16, 32, 64, or 128.

Some registers are special purpose. Other registers are conventionally special. The rest are general purpose.

The Address Space

• The bus defines an n-bit address space with addresses from 0 to 2ⁿ - 1.
  • For example, if n = 16, then 0 to 2¹⁶ - 1 = 65,535 (a.k.a. 64KB).
• Each address references a word, the smallest addressable unit.
  • A word is a 2^m-bit value, 2 \(\leq\) m \(\leq\) 6.
• Words can be picked apart by other, non-addressing, operations.

Address Segments

• Address spaces are partitioned into segments with contiguous address blocks.
  • The segments are dedicated to specific purposes.

Each segment gets its own address range. A segment may be further subdivided into other (sub-)segments.

Bus Fetch-Store

• The bus supports two operations: fetch and store.
  • Fetch accepts an address A returns the value at A.
  • Store accepts an address A and a value V and stores V at A.
• Conceptually,

  Fetch A	: X = bus[A]
  Store V A	: bus[A] = V

Interrupts

• An interrupt is a signal sent from a device to the CPU.
  • It is an asynchronous signal, sent without CPU intervention.
• Interrupts signal an interesting state of the device.
  • “Operation completed”, or “unrecoverable error”, for example.
• Interrupts are typed; each device (or device family) has an interrupt identifiable to it.

Interrupt Processing

• An interrupt acts like an immediate subroutine call into the operating system.
  • Execution jumps (literally) from user execution to system execution.
• The OS handles the interrupt as required, and resumes the interrupted user execution.
  • Possibly, or it resumes some other user execution (as in round-robin scheduling).
• The interrupt type determines the OS interrupt-handler code executed.

Exceptions

• Exceptions are similar to interrupts, but have non-device origins.
  • The OS can generate a quota-exceeded exception.
  • A user process can generate a division-by-zero or invalid-address exception.
• Exception handling can be folded into interrupt handling.

Execution Modes

• Most CPUs allow code to run in one of several execution (or protection) modes.
• Hardware supports least two modes: user (protected, slave, unprivileged) and system (kernel, supervisor, master, unprotected, privileged).
  • Code in system mode can do anything.
    • Access any address and execute any instruction.
  • Code in user mode is restricted.
    • Some addresses are inaccessible, some instructions are unexecutable.

Setting the Mode

• PSW bits determine the execution mode.
• The system boots into system mode.
• Interrupts and exceptions also put execution into system mode.
• “Returning from the interrupt” puts the system in user mode.
  • The return part of the interrupt subroutine call.

Device Access

• On the bus, a device looks like a set of registers.
• Each register has its own address in the address space (memory-mapped devices).
• A device register may be
  • read only, a status register, or
  • write only, a command register, or
  • read-write.

Terminal Device

• A terminal device (a TeleTYpewriter) might have three device registers mapped into the address space.

  

Example

On TTY interrupt:

  if bus[TTY.status] == TTY.read ok
    TTY.in buffer[TTY.next in++] = bus[TTY.data]

  else if bus[TTY.status] == TTY.write ok
    if TTY.out buffer size > 0
      bus[TTY.data] = TTY.out buffer[TTY.next out++]
      TTY.out buffer size--      

  else // deal with other TTY status values

Summary

• Hardware components are interconnected by a bus.
  • Forming a simple linear address space.
• Interrupts and exceptions provide asynchronous signaling between resources.
  • Either hardware (interrupts) or software (exceptions).
• Code executes in either user or supervisor mode.
  • Operating systems in supervisor mode.

References

• An Overview of the Machine and Run-Time Environment (chapter 3) in Operating System Design by Douglas Comer, CRC Press, 2012.

---

This page last modified on 2012 January 28.